As is known, low voltage differential signaling (LVDS) is a standardized data transmission format that is widely used for serial data transmissions. Such LVDS formatting is generally illustrated in FIG. 1. As shown in FIG. 1, a differential signal is centered about a common mode voltage of 1.25 volts. The magnitude of the differential signal is 0.4 volts. As such, with respect to ground, the LVDS signal varies in magnitude from 1.05 volts to 1.45 volts.
One common embodiment of an LVDS driver is illustrated in FIG. 2. As shown in FIG. 2, the LVDS driver includes a P-channel current source, two P-channel input transistors, two N-channel input transistors and an N-channel current source. In addition, the LVDS driver may include impedance matching resistors to provide a desired output impedance, for example the resistors may be 50 Ohm resistors. In operation, the P-channel input transistors and the N-channel input transistors steer the current produced by the P-channel current source (ID) to a load via the output terminals (Vout—n and Vout—p) and the resistors to the N-channel transistor current source. As such, when the positive leg of the differential input signal (Vin—p) is high with respect to the negative leg (Vin—n) the current ID flows through the P-channel transistor with Vin—n as its gate input through the resistors and the load to the N-channel transistor with its gate coupled to Vin—p to the N-channel current source. When the negative leg of the differential signal input (Vin—n) is high with respect to the positive leg of the differential input signal (Vin—p), the current flows through the other pair of P and N-channel transistors.
The LVDS driver of FIG. 2 works well when the supply voltage (VDD) is 3.3 volts or greater, which is common for 0.35 micron CMOS technology. But when the supply voltage drops below 2 volts (e.g., 1.8 volts for 0.18 micron CMOS technology), the LVDS driver of FIG. 2 does not have enough supply voltage headroom for the stacked P-channel transistors. For instance, with reference to FIGS. 1 and 2, as shown in FIG. 1, the signal swings from 1.05 volts to 1.45 volts in magnitude with reference to ground, centered at a common mode voltage of 1.25 volts. If, as allowed by the LVDS standard, the common mode voltage drifts to its upper limit (e.g., increases by 10%), it becomes 1.37 volts, which now raises the magnitude of the differential signal to range between 1.17 volts and 1.57 volts with respect to ground. With a 1.8 volt supply, there is only 0.23 volts of headroom for the drain-source voltage for two P-channel transistors, which is insufficient. This problem is further accentuated when the supply voltage is less than 1.8 volts (e.g., 1.6 volts, 1.1 volts, et cetera).
The LVDS driver of FIG. 3 overcomes the reduced power supply voltage issue by eliminating the stacked P-channel transistor configuration of the embodiment of FIG. 2. In the embodiment of FIG. 3, the LVDS driver includes 2 P-channel current source transistors, 2 N-channel input transistors and an N-channel current source transistor. In this embodiment the P-channel transistors function as fixed current sources to provide current to the load via the N-channel transistors, which are oppositely enabled based on the differential input signal. In this embodiment as shown, the N-channel current source is required to sink twice the current as the corresponding N-channel current source in the embodiment of FIG. 2. Accordingly, the embodiment of FIG. 3 consumes more power than the embodiment of FIG. 2. In addition, the N-channel input transistors are required to be significantly larger in die area than the corresponding N-channel transistors in the embodiment of FIG. 2. If an integrated circuit includes a plurality of LVDS drivers, the increased power consumption and increased die area requirement of the embodiment of FIG. 3 are unacceptable.
Therefore, a need exists for a low power LVDS driver that operates at very low supply voltages.